1. Field of the Invention
The present invention relates to the field of integrated circuit testing and, more particularly, to a technique for performing register-transfer-level scan selection.
2. Background of the Related Art
It is generally known in the semiconductor industry that the testing of integrated circuits comprising thousands or millions of transistors requires complex techniques and specialized test equipment. For example, in a typical processor chip, such as the processors manufactured by Intel Corporation, a variety of different devices are fabricated on a chip. Execution units (both integer and floating point), regular memory, cache memory, register files, decoders, buffers, buses, as well as other circuitry are resident on chip. Thus, the complexity of testing such devices has magnified as more transistors and functions are placed on the chip.
One common method for testing integrated circuits is the use of scan design techniques. In a typical scan technique, specialized circuits are designed into the chip and activated when a test mode is enabled. The activation of the test mode permits a variety of test inputs to be made through the specially designed test circuitry. Then, the integrated circuit is operated under normal mode for one or more clock cycles. Subsequently, the test mode is enabled again and some of the contents of registers and sequential elements internal to the integrated circuit (or portion thereof) are scanned out of the circuit, which is then monitored to determine if the correct results are noted.
A full scan selection technique will test most of the nodes in the circuit to determine the validity of the device, since all sequential elements are made controllable and observable using the scan design. However, full scan selection requires considerable chip space to include the scan design-for-test circuitry required for the scan. In lieu of full scan, partial scan selection techniques have been devised to scan only some of the sequential elements in the circuit. For example, U.S. Pat. No. 5,043,986 describes a method for partial scan testability.
When partial scan selection is utilized for testing, the manner in which circuits are to be scanned can determine the performance of the test technique and the quality of the test generated. For example, the U.S. Pat. No. 5,043,986 patent teaches the elimination of cycles (feedback paths) of desired length to select only a small fraction of the total memory elements of a circuit. Other methodologies develop on partial scan selection to identify which circuits are to be included in the scan path. See for example, "Incomplete Scan Path With An Automatic Test Generation Methodology" by Erwin Trischler, IEEE Test Conference, pp. 153-162, 1980; "On Determining Scan Flip-Flops in Partial-Scan Designs" by D. H. Lee et al., IEEE, pp. 322-325, 1990; "A New Test Generation Method for Sequential Circuits" by D. H. Lee et al., IEEE, pp. 446-449, 1991; "Integrating Scan Into Hierarchical Synthesis Methodologies" by J. Beausang et al.; International Test Conference, IEEE, pp. 751-756, 1996; "Peripheral Partitioning and Tree Decomposition for Partial Scan" by A. Balakrishnan et al., IEEE, pp. 181-186, 1997; and "H-Scan+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs" by Toshiharu Asaka et al., International Test Conference, IEEE, pp. 265-274, 1997.
Although a variety of methodologies exist for partial scan of integrated circuits for testing purposes, the prior art design techniques operate at the circuit level. That is, design criteria for the selection of the sequential circuit components which are to be modified for scanning are performed at the logic gate level. For example, the U.S. Pat. No. 5,043,986 patent provides a method of partial scan design for chip testing, in which the selection of scan memory elements eliminates cycles in the circuit while the circuit is in a test mode. By eliminating cycles of desired lengths, the set of scan memory elements may be only a small fraction of the total memory elements of a circuit. Accordingly, the scan selection looks to the scanning of certain selected circuit components at the logic gate level. The gate level circuit is one that consists of various types of logic gate level elements (such as AND, OR, NAND, etc., inverters, latches and flip-flops).
Although the partial scan selection of circuit components at the logic gate level can provide for optimized presence and usage of test circuitry on integrated circuit chips, it can become very cumbersome to implement in very dense chips, such as a processor chip. Due to a very large number of elements present in a logic gate level netlist, conventional gate level tools take a significant amount of time to select a scan configuration. Register-transfer-level (RTL), on the other hand, is a design specification which is a hierarchy above the circuit level and is utilized extensively for the design of processor chips. It would be advantageous to adapt a scan selection design technique for use at the RTL.
A disadvantage of using the previously known logic gate level partial scan selection techniques is illustrated in FIGS. 1-3. In FIG. 1, a number of gate level sequential circuit elements 10a-c and 11a-c associated with a particular logic circuit 12 (such as a combinational logic) are shown. Sequential circuit elements 10a-10c provide the inputs to the logic circuit block 12. The circuit elements 11a-c are coupled to receive as inputs a set of output from the logic block 12. After capturing them, the elements 11a-c generate outputs that are fed as inputs to another logic circuit 13. The outputs of the elements 11a-cwill depend on the values transferred from the elements 10a-c and input signal(s) to the logic block 12. The outputs of the logic circuit block 13 are then coupled back to the elements 10a-10c to change the values (or status) of these elements. Thus, in normal operation, the input signals are processed by the logic block 12, along with the signal values from elements 10a-10c, to generate output signal(s) from the logic block 12, as well as the signal changes that are captured by the sequential elements 11a-c. A similar sequence of events occurs with the elements 11a-c and logic block 13 to generate signals back to elements 10a-c.
When current methodologies for partial scan selection are used, some of the gate level elements are selected. In the illustration, elements 11a, 11c and 10b are scanned, typically in a sequential fashion. This is shown by the dotted line coupling the three shaded elements. The shading indicates the elements selected for scanning, which elements (or cells) 11a, 11c and 10b will include test circuitry necessary to execute the scan (or test) a variety of such test circuitry are known in the art for performing the scan, including the test circuits described in the earlier-mentioned U.S. Pat. No. 5,043,986 patent. In the test mode, a scan signal (SCAN IN) is coupled to the three selected elements 11a, 11c and 10b and the output (SCAN OUT) of the last sequential cell is used to read the test results This is done by first loading the sequential cells 11a, 11c and 10b in a serial fashion like a shift register whose input is (SCAN IN). This forms the basis of the scan. The clock is pulsed through a certain number of cycles. The resulting values captured in the scan sequential elements 11a, 11c and 10b are then shifted out in a serial fashion and observed at the output (SCAN OUT). This is the general technique of operating scan at the logic gate level. Again a variety of techniques are known for making the selection of a portion of the flip-flops, latches and logic gates present on the chip.
A disadvantage of this approach is shown in FIG. 2. In FIG. 2, the various gate level logic elements are shown formed into a register. A register format is any configuration of bits or data which are manipulated together at a higher level of abstraction. For example, bits forming an instruction word or a set of bits which represent a number are often manipulated as a single, unified higher level entity. The set of sequential elements defined by the same name in a high level description are referred to as registers. Registers are typically multi-bit (although registers can exist as single bit registers), and the content of the register is operated on in a single operation, such as the execution of an instruction. For example, in an adder, contents of one register are added to the contents of another register and the result is placed in one of the two original registers or a third register. The concept and the use of registers and register files are known in the art.
FIG. 2 illustrate the use of two registers 17 and 18 (shown as 8-bit registers), wherein the contents of the registers 17, 18 are processed by a logic circuit 19. It is appreciated that each of the bits of the registers are stored in a gate level sequential component, often known as latches or flip-flops. Thus, when "bits" are discussed below, it is understood that the bits represent some individual circuit component whose state represents the value of the bit. Accordingly, when a prior art gate-level partial scan selection methodology is utilized on a set of bits configured into a register, only some of the bits of the register may get selected for scan. Thus, in the example, bits that are scanned are shown in large blocks to designate the presence of a test circuitry 15 (also shown as "T"), which is utilized in the scan mode. In the illustration, bits 2, 3 and 7 are the scanned bits in the register 17 (also referred to as REG R) and bits 1, 3 and 6 are the scanned bits in the register 18 (also referred to as REG S), while other bits in these registers 17,18 are non-scan bits.
In the illustration, the bits of REG R and REG S are coupled to a logic circuit 19 and subsequently one set of outputs from the logic block 19 are coupled to a register 20 (also referred to as REG T). Next, the lower bits 3:0 of REG T are coupled to a logic circuit 21 and the upper bits 4:7 are coupled to a logic circuit 22. A set of outputs from the logic circuit blocks 22 and 21 are also coupled back to the registers REG R and REG S, respectively. The particular configuration is shown as an example to illustrate the selection of individual elements of a register when prior art scan selection techniques are utilized in the scan design.
As noted in FIG. 2, some of the bits within a register are designated as scanned bits, while others are not. This results from the use of existing gate-level scan methodologies that are employed for partial scan selection. The resulting configuration requires for each individual bit to be separately assigned a scan property. A problem with this approach is that higher level design and test methodologies cannot be effectively implemented using these design-for-test specifications. That is, a state signal representing a register (such as REG T) cannot be described in the RTL as a single signal vector.
In FIG. 2, the bits are shown arranged into registers. Accordingly, a scan signal flow analysis graph (S-Graph) for implementing the scan selection methodology using one of the prior art scan selection techniques may result in the graph shown in FIG. 3. In FIG. 3, bit [7] of REG R is shown connected to bits [7:0] of REG T, to indicate that the value of this bit scan impacts the value of any of the bits in REG T. Likewise, bit [7] of REG T. is shown connected to all bits [7:0] of REG R to indicate its effect in the feedback to all of the bits in REG R. It is appreciated that connections of the other bits are not shown, but it is understood that similar connections are utilized based on the diagram of FIG. 2. Thus, each bit of REG. R and REG S would connect to each bit of REG T in the signal flow graph. Also, bits [7:4] of REG T will connect to all bits of REG R, while bits [3:0] will connect to all bits of REG S.
Accordingly, as noted in the S-Graph diagram of FIG. 3, the scan selection technique employed at the logic gate level results in a complex and cumbersome analysis, since the design mandates the scan selection and signal flow vectors at the individual bit level. When employing the prior art design for scan selection, the device specification contains hardware description-language constructs that have a one-to-one correspondence with the physical latch or flip-flop representations in the circuit. It is appreciated that a significant advantage would result from a design technique which would take into account the scan selection based on a higher level of the hierarchy than at the gate level.